Overview of Semiconductor I/O Interconnect Evolution

Abstract

In the history of IC industry, the trajectory of semiconductor technology is never just about transistor scaling, and it has also been defined by the parallel evolution of input/output (I/O) interconnects, which increasingly dictate system-level performance, power efficiency, and scalability. While on-chip interconnects govern signal latency and bandwidth within integrated circuits, off-chip interconnects define the efficiency of communication across dies, packages, and systems. Traditional off-chip interconnections relied on wire bonding, but controlled collapse chip connection (C4) solder bumps later become the mainstream in flip-chip technologies, which provided high-density interconnects and robust packaging for high-volume manufacturing. The off-chip interconnect technology has been constantly evolving toward finer pitch to achieve higher density and better electrical performance and enabled the rise of 2.5D and 3D integration eventually. Today, more advanced schemes such as copper-to-copper (Cu-to-Cu) interconnects and hybrid bonding offer ultra-fine pitch, low-resistance, and high-reliability vertical stacking, opening the door to next level integration of logic, memory, and heterogeneous chiplets.

Bio

Dr. Bing Dang is a Senior Research Scientist and the Manager of the Electronics and Advanced Packaging Group of Microelectronics Research Lab (MRL) at IBM T. J. Watson Research Center. He has more than 20 years of research and development experience in semiconductor packaging, 2.5D/3D IC and heterogeneous integration, microfluidic cooling, laser-assisted processing, as well as bio-medical device miniaturization. Dr. Dang holds a Ph.D. in Electrical & Computer Engineering from Georgia Tech. He has authored over 75 peer-reviewed technical publications and holds more than 150 granted patents. His research contributions have been featured in EE Times, Chip Scale Review, and Semiconductor Manufacturing Magazine and he received numerous paper awards at IEEE internation conferences over the years. He was named IBM Master Inventor in 2019 and received the prestigious IEEE EPS Exceptional Technical Achievement Award in 2020. Dr. Dang has also been actively contributing to the academic and professional community. He is currently an IEEE Senior Member and served at various leadership positions including the Associate Editor of IEEE Transactions on Advanced Packaging, the Chair of IEEE EPS M&P Technical Committees, ECTC M&P sub-Committee Chair, ECTC 3D Workgroup Chair, and the Publicity Chair for the IEEE International Conference on Digital Health, etc.