Enabling Technology Integration & Product Differentiation: Opportunities in Electronic Packaging

Speaker: Dr. Gaurang Choksi
Retired Vice-President ofTechnology Development Intel Corporation

Technology advances in electronic packaging have supported and sustained Moore’s Law scaling in silicon and have evolved to become important enablers of product performance. The growing demands in computing, data management, AI, and analytics applications drive the need for increased technology integration and customer specific product differentiation. This amplifies the focus on accelerating innovation in the areas of computing, memory, networking, and communication. Consequently, an extremely diverse set of 2.5D/3D heterogenous packaging architectures and designs will emerge, requiring novel constructs, new materials technologies, innovative modeling and simulation tools, test & measurement methods, and manufacturing processes.

This area of high-performance heterogeneous integration will continue to require significant improvements in the collaterals required to meet the challenge to enable high-performance, cost-effective technologies. This includes appropriate and new metrology tools and methods; techniques for analysis & characterization; and multi-variate optimization of design, materials, manufacturing and test process parameters. To address feature size scaling and multi-material systems/interfaces, novel sensors, data analytics, and industry standards for metrologies are critical for fundamental quantification and understanding. These advancements will also accelerate manufacturing process development through techniques such as process simulation and the use of digital twins. The areas of materials characterization and performance validation range across multiple domains such as structural reliability, signal integrity, power delivery, and thermal dissipation need to be reviewed. New interconnect architectures such as optical co-packaging will need new competencies and cross-functional teams for appropriate trade-offs and cost-performance optimization.

BIOGRAPHY

Dr. Gaurang Choksi received his Ph.D. from Virginia Tech in 1988 and recently retired as a Vice-President in the Technology Development organization at Intel Corporation. During his 36+ year tenure at Intel, he worked on a broad range of areas related to electronic packaging and assembly. His experience includes structural integrity and reliability, power delivery, high-speed signaling, thermal management, fluid flow, and co-packaged optics. His contributions span across new experimental methods and metrologies, design tool development, materials selection and characterization, dimensional measurements, and advanced modeling and lab-based validation to support technology selection / development, and assembly process optimization. He received an Intel Achievement Award and serves on academic and other advisory boards.